1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a multiple power supply. In particular, the present invention relates to a level shifter for converting a signal depending on a power supply into a signal depending on another power supply, and a buffer circuit including the level shifter.
2. Description of the Related Art
In a semiconductor integrated circuit, particularly, in an LSI (Large Scale Integrated circuit), a power supply voltage provided for internal circuits has been progressively reduced to lower level, because of a drop in a surge voltage capacity associated with an advancement in a high integrated fine process and a requirement for reducing an electric power consumption. On the other hand, a signal voltage level of an external input-output terminal of the LSI connected to an external device depends on characteristics of the external device and includes a variety of levels. Therefore, it is necessary in the LSI to provide another power supply voltage different from the power supply voltage for the inner circuits.
As a result, a plurality of power supply voltages are provided in one LSI chip. Thus, a circuit unit known as a “level shifter” is necessary for interfacing a power supply region with another power supply region on the LSI chip. The level shifter converts a signal level of a signal in the LSI chip.
FIG. 1 is a circuit block diagram showing an output buffer including level shifters (LS) and a tri state buffer. A region RI corresponds to an LSI internal region to which a low power supply voltage VDD2 is provided, while a region RE corresponds to an LSI external interface region to which a high power supply voltage VDD3 is provided. The low power supply voltage VDD2 is an internal voltage and is supplied to internal circuits. On the other hand, the high power supply voltage VDD3 is an external interface voltage and is supplied to external interface circuits. For example, the low power supply voltage VDD2 is 2.5 V, and the high power supply voltage VDD3 is 3.3 V which is higher than the low power supply voltage VDD2.
The output buffer has a first level shifter 11, a second level shifter 12, and a tri state buffer 13. The tri state buffer 13 is provided in the region RE. The first level shifter 11 receives a data signal from a data input terminal D_in. The first level shifter 11 converts a signal level of the received data signal, and then outputs the level-shifted data signal to the tri state buffer 13. For example, the first level shifter 11 converts a high-level data signal of 2.5 V in the region RI into a high-level data signal of 3.3 V in the region RE. The second level shifter 12 receives an enable signal from an enable control input terminal D_En. The second level shifter 12 converts a signal level of the received enable signal, and then outputs the level-shifted enable signal to the tri state buffer 13. The enable signal is a signal for enabling the tri state buffer 13. An output of the tri state buffer 13 is dependent on the data signal and the enable signal. That is, the output status of the tri state buffer 13 becomes any of High, Low, and High Impedance in accordance with the data signal and the enable signal.
Each of the first level shifter 11 and the second level shifter 12 has the same configuration. FIG. 2 is a circuit diagram showing the configuration of the level shifter according to the conventional technique. As shown in FIG. 2, the level shifter (LS) has an inverter 21, a voltage converting circuit 22, and a buffer 24.
The inverter 21 is connected to an input terminal In of the level shifter. The low power supply voltage VDD2 is supplied from a first power supply to the inverter 21. The inverter 21 has a P-channel transistor and a N-channel transistor which are connected in series between the power supply VDD2 and the ground. The inverter 21 receives an input signal from the input terminal In, and inverts the input signal to generate an inversion signal.
The voltage converting circuit 22 includes P-channel transistors 201, 202, and N-channel transistors 203, 205. Sources of the P-channel transistors 201, 202 are connected to a second power supply which supplies the high power supply voltage VDD3. Drains of the P-channel transistors 201 and 202 are connected to nodes 207 and 208, respectively. A gate of the P-channel transistor 201 is connected to the node 208, and a gate of the P-channel transistor 202 is connected to the node 207. In other words, the P-channel transistor 201 and the P-channel transistor 202 are cross-coupled. Also, sources of the N-channel transistors 203, 205 are connected to the ground. A drain of the N-channel transistor 203 is connected to the node 207 and hence to the gate of the P-channel transistor 202. A drain of the N-channel transistor 205 is connected to the node 208 and hence to the gate of the P-channel transistor 201. A gate of the N-channel transistor 203 is connected to the input terminal In, and the input signal to the level shifter is applied to the gate of the N-channel transistor 203. A gate of the N-channel transistor 205 is connected to the output of the inverter 21, and the inversion signal is applied to the gate of the N-channel transistor 205. The node 208 is connected to an output of the voltage converting circuit 22. Due to the voltage converting circuit 22, the signal level of the input signal inputted to the input terminal In is converted to match the high power supply voltage level VDD3, and the level-shifted signal is outputted from the node 208 to the buffer 24.
The buffer 24 is connected between the output of the voltage converting circuit 22 and an output terminal Out of the level shifter. The buffer 24 includes two-stage inverter, and the high power supply voltage VDD3 is supplied to the two-stage inverter. The level-shifted signal is outputted from the output terminal Out as an output signal.
When the low and high power supply voltages VDD2 and VDD3 are normally supplied, complementary signals are applied to the respective gates of the N-channel transistors 203 and 205. Also, signal levels at the nodes 207 and 208 are determined.
For example, when the signal level of the input signal is High (2.5 V), the N-channel transistor 203 is turned ON, while the N-channel transistor 205 is turned OFF. Thus, the voltage level of the node 207 is changed to Low, and the voltage level of the node 208 is changed to High. The P-channel transistor 202 whose gate is connected to the node 207 is turned ON, while the P-channel transistor 201 whose gate is connected to the node 208 is turned OFF. Thus, the voltage level of the node 208 is settled to High (3.3 V). The voltage level of the node 208 is transmitted through the buffer 24 to the output terminal Out. As a result, the signal level of the High signal (2.5 V) inputted to the input terminal In is converted to 3.3 V, and the High signal (3.3 V) is outputted from the output terminal Out. As described above, the circuit shown in FIG. 2 functions as a level shifter as a whole. When the signal level of the input signal is Low (0 V), a Low signal (0 V) is outputted from the output terminal Out due to a similar operation.
Here, let us consider a situation when the first power supply is turned OFF and only the second power supply is turned ON. In this case, the low power supply voltage VDD2 is 0 V, although the high power supply voltage VDD3 is 3.3 V. Such a situation can occur for a short time (in an order of msec) and over a long time, when a system is powered on, a multi power supply circuit is used, the system is failed, and so on.
When the first power supply is turned OFF and the low power supply voltage VDD2 is 0 V, a signal from a circuit system depending on the first power supply become 0V or a low level close to 0V. In the circuit shown in FIG. 2, the voltage levels of the gates of the N-channel transistors 203 and 205 become Low, and both of the N-channel transistors 203 and 205 are turned OFF. In this case, the voltage level of the node 207 is High or High Impedance, which is unstable. Also, the voltage level of the node 208 is High or High Impedance, which is unstable. Thus, the signal level of the output signal outputted from the output terminal Out is also unstable. When the level shifters 11, 12 shown in FIG. 1 are in such a status and the unstable output signals are inputted to the tri state buffer 13, some unexpected signals which are not assumed in a system designing may be outputted from the output terminal D_out to the outside of the LSI chip. Such unexpected signals can cause unexpected system failure.
In order to solve such a problem, Japanese Laid Open Patent Application (JP-P2001-144600A) discloses another level shifter, in which drop in the low power supply voltage VDD2 (inner voltage) is sensed, and the status of the level shifter is reset to stabilize the voltage level of the output terminal Out.
FIG. 3 is a circuit diagram showing a configuration of the level shifter according to the conventional technique disclosed in the above-mentioned patent document (JP-P2001-144600A). As shown in FIG. 3, the level shifter (LS) has an inverter 31, a voltage converting circuit 32, a Schmitt-Trigger inverter 33, and a buffer 34.
The inverter 31 is connected to an input terminal In of the level shifter. The low power supply voltage VDD2 is supplied from a first power supply to the inverter 31. The inverter 31 has a P-channel transistor and a N-channel transistor which are connected in series between the power supply VDD2 and the ground. The inverter 31 receives an input signal from the input terminal In, and inverts the input signal to generate an inversion signal.
The voltage converting circuit 32 includes P-channel transistors 301, 302, and N-channel transistors 303, 305 and 306. Sources of the P-channel transistors 301, 302 are connected to a second power supply which supplies the high power supply voltage VDD3.
Drains of the P-channel transistors 301 and 302 are connected to nodes 307 and 308, respectively. A gate of the P-channel transistor 301 is connected to the node 308, and a gate of the P-channel transistor 302 is connected to the node 307. In other words, the P-channel transistor 301 and the P-channel transistor 302 are cross-coupled. Also, sources of the N-channel transistors 303, 305 and 306 are connected to the ground. A drain of the N-channel transistor 303 is connected to the node 307 and hence to the gate of the P-channel transistor 302. Drains of the N-channel transistors 305 and 306 are connected to the node 308 and hence to the gate of the P-channel transistor 301. A gate of the N-channel transistor 303 is connected to the input terminal In, and the input signal to the level shifter is applied to the gate of the N-channel transistor 303. A gate of the N-channel transistor 305 is connected to the output of the inverter 31, and the inversion signal is applied to the gate of the N-channel transistor 305. A gate of the N-channel transistor 306 is connected to the output of the Schmitt-Trigger inverter 33. The node 308 is connected to an output of the voltage converting circuit 32.
The buffer 34 is connected between the output of the voltage converting circuit 32 and an output terminal Out of the level shifter. The buffer 34 includes two-stage inverter, and the high power supply voltage VDD3 is supplied to the two-stage inverter. The level-shifted signal is outputted from the output terminal Out as an output signal.
FIG. 4 shows a configuration of the Schmitt-Trigger inverter 33 (refer to FIG. 2 in the above-mentioned patent document JP-P2001-144600A). The Schmitt-Trigger inverter 33 has a hysteresis characteristic. As shown in FIG. 4, the Schmitt-Trigger inverter 33 has a level shifter 41, inverters 42 and 43, and a P-channel transistor 402. Sources of P-channel transistors of the level shifter 41 are connected to the second power supply (VDD3). A gate of a N-channel transistor 401 of the level shifter 41 is connected to the first power supply (VDD2). A drain and source of the N-channel transistor 401 are connected to a node 410 and the ground, respectively. The node 410 is connected to an input of the inverter 42 through a node 420. An output of the inverter 42 is connected not only to an input of the inverter 43 but also to a gate of the P-channel transistor 402. A source of the P-channel transistor 402 is connected to the second power supply (VDD3). A drain of the P-channel transistor 402 is connected to the node 420, i.e., to the input of the inverter 42. An output of the inverter 43 is connected to an output terminal Out.
When the first power supply supplies the voltage VDD2 normally, the N-channel transistor 401 is turned ON and hence the voltage level of the node 410 is set to Low. Thus, a low level signal is outputted from the output terminal Out of the Schmitt-Trigger inverter 33. Next, let us consider a situation when the first power supply (VDD2) is turned OFF and only the second power supply (VDD3) is turned ON. Such a situation can occur, for example, when a system is powered on. In this case, the low power supply voltage VDD2 is 0 V, and the N-channel transistor 401 is turned OFF. At the time when the system is powered on, the gate voltages of the P-channel transistors of the level shifter 41 tend to be 0 V. Therefore, the P-channel transistors of the level shifter 41 are turned ON, and thus the voltage level of the node 410 begins to increase. Then, a N-channel transistor of the inverter 42 is turned ON at a certain timing, and the inverter 42 outputs a low level signal to the gate of the P-channel transistor 402. As a result, the P-channel transistor 402 is turned ON, and hence the voltage of the node 420 is determined to be the high power supply voltage VDD3. Therefore, a high level signal is outputted from the output terminal Out.
As described above, the Schmitt-Trigger inverter 33 outputs a low level signal (0 V) when the first power supply (VDD2) is switched on. On the other hand, the Schmitt-Trigger inverter 33 outputs a high level signal (3.3 V) when the first power supply (VDD2) is switched off. The low level signal and the high level signal are applied to the gate of the N-channel transistor 306 shown in FIG. 3. As described below, the N-channel transistor 306 plays a role of resetting the level shifter shown in FIG. 3.
Now referring to FIG. 3, when the low power supply voltage VDD2 is normally supplied, a low level signal is applied to the gate of the N-channel transistor 306 and the N-channel transistor 306 is turned OFF. From a view point of D.C., such a situation is equivalent to a situation where the N-channel transistor 306 does not exist. Therefore, the cross-coupled P-channel transistors 301 and 302, the N-channel transistors 303 and 305 connected to respective of the nodes 307 and 308, and the inverters 31 and 34 function as a level shifter as in FIG. 2.
On the other hand, when the first power 20 supply is turned OFF and the low power supply voltage VDD2 is 0 V, both of the N-channel transistors 303 and 305 are turned OFF. However, the Schmitt-Trigger inverter 33 outputs the high level signal (3.3 V) to the gate of the N-channel transistor 306, and hence the N-channel transistor 306 is turned ON. Therefore, the voltage level of the node 308 is determined to Low, and thus the voltage level of the output terminal Out of the level shifter is fixed to Low. According to the conventional art, as explained above, the signal level of the output signal outputted from the level shifter is fixed to Low when the low power supply voltage VDD2 is 0 V, which prevents the unstable and unexpected output signal.